Analog Devices’ low jitter synthesiser enables high performance in GSPS data converter solutions
13 July 2022
Analog Devices, Inc. has introduced an 800MHz to 12.8GHz synthesiser for high performance ultra-wideband data converter and synchronisation applications.
The new ADF4377 synthesiser enables excellent signal-to-noise performance by providing an ultra-clean clock source to drive the signal sampling process. This allows next generation wideband receivers and transmitters to utilise higher levels of dynamic range, which leads to greater receiver sensitivity and transmitter spectral purity.
The performance is achieved by the ADF4377 synthesiser delivering jitter levels below 18fs rms as a consequence of the low normalised in-band phase noise at -239dBc/Hz, -147dBc/Hz normalised 1/f noise, and a wideband voltage control oscillator (VCO) noise floor of -160dBc/Hz.
The ADF4377 synthesiser is suitable for applications such as radar, instrumentation, and wideband receivers requiring multiple data converters or mixed-signal front-end (MxFE) digitisers to operate together. The ADF4377 significantly simplifies the alignment and calibration routines by allowing groups of data converters to sample their signals in precise alignment with each other. This is fundamental to the operation of next generation ultra-wideband multi-channel systems and is achieved by implementing:
• Automatic reference to output synchronisation.
• Extremely well-matched reference to output delays across process (3ps part to part), voltage, and temperature (0.03ps/C).
• Sub-ps, jitter free reference to output delay adjustment capability (+/- 0.1ps).
These features allow for predictable and precise multi-chip clock and SYSREF alignment. JESD204B and JESD204C subclass 1 solutions are supported by pairing the ADF4377 synthesiser with an IC that distributes pairs of reference and SYSREF signals. The ADF4377 integrates all necessary power supply bypass capacitors, saving board space on compact boards.
ADF377 Key Features:
• Output frequency range: 800MHz to 12.8GHz
• Jitter = 18fs rms (Integration BW: 100Hz to 100MHz)
• Wideband Noise Floor: -160dBc/Hz @12GHz
• PLL Specifications:
o -239dBc/Hz: Normalised In-Band Phase Noise Floor
o -147dBc/Hz: Normalised In-Band 1/f Noise
o Phase Detector Frequency up to 500 MHz
• Reference to Output Delay Specifications:
o Part-to-Part Standard Deviation: 3ps
o Temperature Drift: 0.03ps/?
o Multi-chip Output Phase Alignment
More information available here.
Contact Details and Archive...